The present invention relates to a display panel such as a plasma display panel and a method of producing the display panel.
A display such as a plasma display panel (hereinafter called the PDP) using glass substrates is formed by putting two sheets of glass substrates on top of each other with a predetermined space formed therebetween in order to seal predetermined structural components inside. The structure of a display area (display cell structure) where an image is displayed will be described hereunder by reference to one example already proposed by the present applicant.
FIG. 1 is an exemplary plan view of the display cell structure of the PDP; FIG. 2, a sectional view taken on line V1—V1 of FIG. 1; FIG. 3, a sectional view taken on line V2—V2 of FIG. 1; FIG. 4, a sectional view taken on line W1—W1 of FIG. 1; and FIG. 5, a sectional view taken on line W2—W2 of FIG. 1.
As shown in FIGS. 1 to 5, a plurality of line electrode pairs (X and Y) are arranged in parallel so as to extend in the line direction (lateral direction of FIG. 1) of a front substrate 10 on the back of the front substrate 10 as a display surface in the display area of the PDP. Each line electrode X is formed with a transparent electrode Xa such as a T-shaped transparent conductive film of ITO (Indium Tin Oxide) and a bus electrode Xb of a metal film extended in the line direction of the front substrate 10 and connected to the narrow base end portion of the transparent electrode Xa.
Like the line electrode Y, each line electrode Y is formed with a transparent electrode Ya such as a T-shaped transparent conductive film of ITO (Indium Tin Oxide) and a bus electrode Yb of a metal film extended in the line direction of the front substrate 10 and connected to the narrow base end portion of the transparent electrode Ya.
The line electrodes X and Y are arranged alternately in the column direction (vertical direction of FIG. 1) of the front substrate 10. The pair of transparent electrodes Xa and Ya arranged in a row along the bus electrodes Xb and Yb are respectively extended in the directions of the opposite line electrodes. Moreover, the broad top-side portions of the transparent electrodes Xa and Ya face each other with a predetermined discharge gap g held therebetween.
The bus electrodes Xb and Yb are formed into a two-layer structure having black conductive layers Xb1 and Yb1 on the display surface side and main conductive layers Xb2 and Yb2 on the back side. On the back of the front substrate 10, a black light-absorption layer (shield layer) 30 extending in the line direction along the bus electrodes Xb and Yb is formed between the bus electrodes Xb and Yb sitting back to back with respect to the adjoining line electrode pair (X and Y) arranged in a row direction. Further, a light absorption layer (shield layer) 31 is formed in a portion opposite to the vertical wall 35a of each partition wall 35.
On the back of the front substrate 10, a dielectric layer 11 is formed so as to cover the line electrode pairs (X and Y) and on the back of the dielectric layer 11, a bulked dielectric layer 11A protruding from the back of the dielectric layer 11 is formed so as to extend in parallel to the bus electrodes Xb and Yb in a position opposite to the bus electrodes Xb and Yb adjacent to the adjoining line electrode pair (X and Y) and in a position opposite to the area between the bus electrode Xb and the bus electrode Yb adjacent to each other.
A protective layer 12 of MgO is formed on the back side of the dielectric layer 11 and the bulked dielectric layers 11A. On the other hand, column electrodes D are arranged in parallel at predetermined intervals on the display-side surface of a back substrate 13 arranged in parallel to the front substrate 10 so that each column electrode D is extended in a direction perpendicularly crossing the line electrode pair (X and Y) (in the column direction) in a position opposite to the pair of transparent electrodes Xa and Ya of the line electrode pair (X and Y). On the display-side surface of the back substrate 13, further, a white dielectric layer 14 for covering the column electrodes D is formed and the partition walls 35 are formed on the dielectric layers 14.
The partition walls 35 are formed into the shape of a lattice by the vertical wall 35a extending in the column direction in a position between the column electrodes D arranged in parallel to each other and the horizontal wall 35b extending in the line direction in a position opposite to the bulked dielectric layer 11A. With the lattice like partition walls 35, the space between the front substrate 10 and the back substrate 13 is formed into sections, in each of which the transparent electrodes Xa and Ya are placed opposite to each other in the line electrode pair (X and Y) to form a discharge space S.
The display-side face of the vertical wall 35a of each partition wall 35 is not in contact with the protective layer 12 (see FIG. 4) and a space γ is formed therebetween. However, the display-side face of the horizontal wall 35b is brought into contact with a portion of the protective layer 12, the portion being used to cover the bulked dielectric layer 11A (see FIGS. 2 and 5), so that adjoining discharge spaces S in the column direction are shielded from each other.
A phosphor layer 16 is formed on the vertical walls 35a and the sides of the horizontal walls 35b of the partition walls 35 facing each discharge space S and the surface of the dielectric layer 14 in such a manner as to cover all of these five sides in due order.
The color of the dielectric layers 16 is set R, G and B in the line direction successively in the respective discharge spaces S (see FIG. 4). Moreover, rare gas is enclosed in the discharge spaces S. The horizontal walls 35b1 and 35b2 of each partition wall 35 that separates the discharge space S from another are separated from each other in the column direction by a space SL provided in a position where the light absorption layer 30 between display lines is placed above the space SL.
More specifically, the partition walls 35 are formed into the shape of a lattice along the display lines L and arranged in parallel to each other via the space SL extending along the display lines L in the column direction. The width of the space SL is set so that the width of the portions 35b1 and 35b2 of the horizontal wall 35b separated from each other by the space SL provided between the display lines L becomes substantially equal to the width of the vertical wall 35a. 
In the PDP above, the line electrode pair (X and Y) forms one display line (line) L of a matrix display screen and each of the discharge spaces S separated from each other by the latticelike partition wall 35 is used to determine one subdivided discharge cell C.
The PDP above is produced by laying the front substrate formed with the line electrode pairs, the dielectric layer, the bulked dielectric layers and the protective layer upon the back substrate formed with the column electrodes, the protective layer of the column electrodes, the partition walls and the phosphor layers; by sealing the surrounding of the combination of the substrates; forming a vacuum in the interior space therebetween; and enclosing a discharge gas therein.
However, in case where the structural components formed on both the front and back substrates cause a relative deviation in position when the substrates are stuck together, a normal electric discharge is impeded and good display quality is unavailable. Consequently, positioning marks have been formed outside the display area of the PDP on the substrates whereby to carry out the positioning of both the substrates relatively.
FIG. 6 is a diagram illustrating conventional positioning-mark forming layers. In the display area of the PDP, a cross section taken on line from V1 up to W1 and perpendicularly folded at K of FIG. 1 shows the relation between each layer within the display area and the positioning-mark forming layers formed outside the display area.
As shown in FIG. 6, metal films as bus marks Mb are formed on the outer side 10b of the display area of the front substrate, the bus marks Mb being formed in the same layer as a layer in which the bus electrodes Xb and Yb are formed within a display area 10a. Further, metal films as address marks Ma are formed on the outer side 13b of the display area of the back substrate, the bus marks Ma being formed in the same layer as a layer in which the column electrodes D are formed.
Heretofore, the bus marks Mb and the address marks Ma have been used as positioning marks. As the bus marks Mb and the address marks Ma are formed of metal films, the relative positions of the marks are made detectable by the use of transmissive illumination, so that it is possible to carry out the positioning of the bus electrodes Xb and Yb and the column electrodes D that are formed in the respective mark-positioning layers.
With respect to influence over the performance of the PDP affected by relative deviation in position as mentioned above, importance is directed to the positional accuracy of the transparent electrodes Xa and Ya projected opposite to each other via the discharge gap on a cell basis against the partition wall (especially the vertical wall 35a) or the positional accuracy of the bulked dielectric layer 11A against the partition wall (especially the horizontal wall 35b).
The transparent electrodes Xa and Ya and the bulked dielectric layers 11A are formed on the front substrate 10 with the bus marks Mb as a reference, whereas the partition walls 35 are formed on the back substrate 13 with the address marks Ma as a reference. Therefore, deviation in position caused at the step of formation or deviation in position caused at the step of calcination under the influence of reduction in the size of the substrate tends to occur against each of the marks.
In the PDP formed by carrying out the positioning of both the substrates relatively based on the bus marks Mb and the address marks Ma and sticking the front substrate 10 and the back substrate 13 together, such deviation in position is liable to occur between the transparent electrodes Xa and Ya and the partition wall (vertical wall 35a) or the bulked dielectric layer 11A and the partition wall (horizontal wall 35b).
Further, the influence of deviation in position increases when the display cells are reduced in size so as to cope with sophistication of the PDP, the problem is that the performance of the PDP lowers.